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There is a question when there is undefined instruction .... do we need to obtain current execution instruction from R14_SVC or R14_UNDEF ? . I am currently working on a problem where an undefined command happened. These instructions were found below when I checked R14_SVC: 

  0x46BFD73C cmp r0, # 0x0 0x46BFD740 beq 0x46BFD75C 0x46BFD744 ldr r0,0x46BFE358   
 In my The assumption is that the compulsory instruction would have happened when performing education  beak 0x46 bfd 75c    
, the one thing that would be my puzzle, i  r14_undef < / Code> and the instructions were different.  
  0x46bfd4b8 bx r14 0x46bfd4bc mov r0, 0x01 0x46bfd4c0 bx r14   
 Who caused undefined instructions to create an exception?   
 
 
 All your answers are in ARM ARM, ARM architecture reference manual. Go to infocenter.arm.com under the reference-guide to find the architecture family you are interested in. The non-Cortex-M series handles all these exceptions in the same way.  
  When an unscheduled exception is exempt, the following actions are performed: After the undefined instruction, R14_und = Address: SPSR_und = CPSR CPSR [4: 0] = 0b11011 / * Enter unsupported instruction mode * / CPSR [5] = 0 / * execute in ARM position * / / * CPSR [6] is unchanged * / CPSR [7] ] = 1 / * Disabled Normal Interrupt * / / * * CPSR [8] A Reversed * / CPSR [9] = CP15_reg1_EEbit / * Exception on Exception Entry * / If High Vector is configured then PC = 0xFFFF0004 and PC = 0x00000004   
 In the next instruction after the mandatory instruction R14_und Points You should know what mode is set in the processor (arm or thumb), to know that you have to reduce 2 or 4 by R14_und and if you need 2 or 4 bytes then you should check the SPSR Have to do Unfortunately, if a new architecture that supports Thumb-2, you may have to get 4 bytes in thumb mode and find out what happened. It is possible to do this in the case of variable word length, where it is impossible to determine what happened. If you are not using Thumb 2 instructions then it is deterministic.

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